The present disclosure relates to a semiconductor memory, and more particularly, to configuration of a memory cell array of a semiconductor memory.
The critical dimension (CD) of a volatile semiconductor memory such as a dynamic random access memory (DRAM) may be gradually scaled down according to a demand on high speed, large capacity, and low power.
Although it is difficult to continue to scale down the critical dimension due to a limit to the resolution of photolithography, improvement on the performance of a memory chip may be continuously desired. Also, a large storage capacity and a low-power characteristic may be desired.